According to the Open Systems Interconnection (OSI) reference model defined by the ISO/IEC, the Ethernet Data Link Layer (DL) and the Physical Layer (PHY) are connected through an x MII. A 10M/100M Ethernet interface is an MII, 1000M and higher-speed Ethernet interfaces are Gigabit Media Independent Interfaces (GMIIs), and a 10 GE interface is a 10 Gigabit Media Independent Interface (XGMII).
Besides, the Media Access Control (MAC) layer data is transmitted per byte (8 bits) through an MII bus. Transcoding is performed per byte at the Physical Coding Sublayer (PCS) of the physical layer.
With the progress of time and technologies, the Ethernet develops toward the 100 G rate. Currently, the 100 GE is being standardized. The work of the IEEE HSSG is to: specify the requirements of the High Speed Ethernet (HSE) of 10 G or higher rates, research the market potentiality, technical maturity and economic maturity, determine subsequent standard projects and project objectives, and prescribe the subsequent technical solution research and solution standardization. The 100 GE standardization process needs to be supported by the definition of the 100 Gigabit Media Independent Interface (CGMII) interface.
If the 100 GE continues using the multi-channel byte distribution mode, the order of distributing the byte needs to be maintained in the multi-channel forwarding process so that the subsequent 64B/66B coding of channels is ensured. Moreover, every 8 bits carry a 1-bit control identifier. The increase of data bit width leads to a sharp increase of the control identifier bits. Therefore, if the 100 GE uses the multi-channel byte distribution mode, the signal bit width is small and the distribution unit is small and cannot support data distribution of high-speed interfaces.
The XGMII uses the multi-channel byte distribution mode, namely, uses four channels. One channel distributes 8-bit data signals and 1-bit control signals, thus increasing the bit width of the XGMII interface to 32 bits (4 bytes). The control signal indication mode of MII and GMII is not applicable to the multi-channel control indication. Therefore, control characters are introduced into the XGMII interface. The control signal validity and the control character code jointly indicate the control information and data information: An invalid control signal indicates that the information is data information; and a valid control signal and a control character code jointly indicate the control information on the channel.
However, the 8-bit data character represents control character information when the control line is valid, but the 1-bit control line (TXC) may still only indicate whether the 8 bits are a data character or a control character. Based on the related art, the number of the control lines increases sharply with the increase of the bit width, and the block types are more and more complicated while the PCS performs coding.
In the process of developing the present invention, the inventor finds that in the prior data distribution technology of high-speed interfaces, the number of the control lines increases sharply with the increase of the bit width, and the block types are more and more complicated while the PCS performs coding.